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ARM Cortex-M1 Development Using Altera SoPC Builder

The Cortex-M1 processor is intended for deeply embedded applications that require a small processor integrated into an FPGA. This course is designed for hardware engineers, software engineers, and system engineers who need to learn how to build a complete SOC for an Altera FPGA. It includes a detailed overview of the ARM Cortex-M1 architecture. It also includes a Cortex-M1 Example System Tutorial based on the Cortex™-M1 FPGA Development Kit. The tutorial demonstrates how to build a complete SOC for an Altera FPGA using the Cortex-M1 processor and available Altera SOPC peripheral and bus components. The course content of the tutorial is consistent with typical embedded FPGA processor designs that use a Cortex-M1 processor so that the knowledge gained can be generalized.

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Upcoming

Scheduled ARM Training Courses

Course Info

Course Type:
Hardware and software
Course Length:
4 days
Course Price (1 to 2): 2550
Course Price (3+): 2250

ARM Training

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Prerequisites

  • Familiarity with embedded system hardware and software development
  • Familiarity with digital logic and hardware/FPGA design issues
  • Experience with assembly language programming (not required but helpful)
  • Knowledge of programming in C
  • Some knowledge of Soft Core IP terminology and development tools

Audience

Hardware design engineers who need an introduction on how to model deeply embedded system-on-a-programmable chip (SoPC) designs and software engineers who need to develop and simulate prototype applications. Design engineers who have developed traditional microcontroller-based designs, but now need to move to re-usable IP and soft-core implementations would also benefit.

Objectives

In addition to accurate knowledge of the Cortex-M1 architecture, this course provides an overview of the key issues relating to implementation of a Cortex-M1 design. Upon completion, students should know:

  • How ARM delivers Cortex-M1 Soft-IP
  • How to configure the Cortex-M1 RTL deliverables for a given implementation
  • How to validate Cortex-M1 RTL
  • How to implement Cortex-M1 (Synthesis, place & route, verification)
  • Sign-off Issues
  • Issues regarding IP delivery

Modules

  • ARM Cortex-M1 Architecture
    • Cortex-M1 Introduction
    • Application Programmer's Model
    • Memory Types
    • Interrupts
    • Basic Exceptions
    • Advanced Exceptions
    • System Programmer's Model
    • Clocks, Reset, and Power Management
    • Implementation
    • Debug
    • Instruction Set
    • System Interfaces
  • Example System Tutorial
    • Introduction to the Cortex-M1 Development Kit Tutorial
    • Getting Started
    • Demo Software for Cyclone III Starter Kit and the Example SOPC System
    • Debugging the Example SOPC System with the Realview MDK tools
    • Simulating the Example SOPC System
    • RTX Real Time Operating System Example
    • Example SOPC System and Software Considerations and Customizations
    • Appendix A: Configuring the Example SOPC System (optional)

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